What is Cache Coherence in Multiprocessor Systems?

Learn what cache coherence is — MESI states, snooping vs directory protocols — with multiprocessor OS interview questions answered.

hardQ133 of 224 in Operating Systems Est. time: 6 minsLast updated: July 2026

Open Code Lab

Expected Interview Answer

Cache coherence is the guarantee that all CPU cores in a multiprocessor system see a single, consistent view of a shared memory location, even though each core keeps its own private cached copy, and it is typically enforced by a hardware protocol like MESI that tracks and propagates writes across caches.

Without coherence, if core A writes to a memory address that core B has cached, core B could keep reading its stale cached value forever, silently corrupting shared-state logic — a real bug class in multithreaded programs. Hardware coherence protocols solve this using either a snooping bus, where every cache monitors a shared bus for writes to addresses it holds and invalidates or updates its copy, or a directory-based scheme, where a central directory tracks which caches hold each line and sends targeted invalidation or update messages, which scales better on systems with many cores. The MESI protocol names four states a cache line can be in — Modified (dirty, exclusive to this cache), Exclusive (clean, exclusive to this cache), Shared (clean, possibly cached elsewhere too), Invalid (stale, must be refetched) — and transitions between these states on every local read/write and every snooped remote read/write. Cache coherence must not be confused with memory consistency: coherence guarantees a single agreed value per address, while consistency models (like sequential consistency or relaxed models) govern the order in which different addresses’ updates become visible across cores.

Guarantees a single, consistent value per shared memory address across cores
MESI protocol gives a precise, well-defined state machine for each cache line
Snooping vs directory-based protocols trade off simplicity against scalability
Distinguishes coherence (single value per address) from consistency (ordering across addresses)

AI Mentor Explanation

Cache coherence is like every team’s dressing room having its own whiteboard copy of the current match score: if the scoreboard operator updates the real score, a runner (like a snooping bus) must dash to every dressing room and cross out the old number so no team keeps celebrating a stale total. Without that runner, one dressing room might still show yesterday’s score while another shows the live one — exactly the stale-cache bug coherence protocols prevent. The MESI states mirror whether a room’s whiteboard is the only updated copy, a shared accurate copy, or a now-invalid one needing a refresh.

Step-by-Step Explanation

Step 1
Local cache miss and fetch
A core reads an address, misses in its private cache, and fetches the line, marking it Exclusive or Shared per MESI.
Step 2
Remote write detected
A snooping bus or directory notices another core is about to write the same cache line held elsewhere.
Step 3
Invalidation or update
Other caches holding that line transition to Invalid (invalidate protocol) or receive the new value (update protocol).
Step 4
Re-fetch on next access
A core with an Invalid line must re-fetch it from memory or the writer's cache before its next read, guaranteeing a fresh value.

What Interviewer Expects

A clear definition of coherence as a single consistent value per shared address
Ability to explain at least one enforcement mechanism (snooping bus or directory-based)
Familiarity with the MESI protocol states and why they exist
Correctly distinguishing cache coherence from memory consistency models

Common Mistakes

Conflating cache coherence with memory consistency (they answer different questions)
Thinking software alone (without hardware protocols) maintains coherence
Not knowing what the four MESI states represent
Assuming snooping-bus coherence scales to hundreds of cores without a directory

Best Answer (HR Friendly)

“Cache coherence is what makes sure that when multiple CPU cores each keep their own private copy of the same piece of shared memory, they never disagree about its current value. Hardware protocols like MESI automatically invalidate or update stale copies whenever one core writes, so a program never silently reads outdated data just because it happened to run on a different core.”

Code Example

MESI-style state transition sketch for a cache line

enum mesi_state { INVALID, SHARED, EXCLUSIVE, MODIFIED };

struct cache_line {
    unsigned tag;
    enum mesi_state state;
    long data;
};

/* Local write, assuming the line is currently Shared or Exclusive */
void local_write(struct cache_line *line, long value) {
    if (line->state == SHARED) {
        broadcast_invalidate(line->tag);   /* tell other caches to drop their copy */
    }
    line->data  = value;
    line->state = MODIFIED;                /* dirty, exclusive to this cache */
}

/* Snooped remote write to an address this cache holds */
void on_snoop_invalidate(struct cache_line *line, unsigned tag) {
    if (line->tag == tag && line->state != INVALID) {
        line->state = INVALID;             /* stale copy must be re-fetched next time */
    }
}

Follow-up Questions

What is the difference between a snooping-bus and a directory-based coherence protocol?
What do the four MESI states (Modified, Exclusive, Shared, Invalid) each represent?
How does cache coherence differ from a memory consistency model?
Why does directory-based coherence scale better on many-core systems than snooping?

MCQ Practice

1. What problem does cache coherence solve?

2. In the MESI protocol, what does the "Modified" state mean?

3. What distinguishes cache coherence from memory consistency?

Flash Cards

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What is Cache Coherence in Multiprocessor Systems?

Expected Interview Answer

AI Mentor Explanation

Step-by-Step Explanation

Local cache miss and fetch

Remote write detected

Invalidation or update

Re-fetch on next access