Make & Makefiles Cheat Sheet
GNU Make syntax for defining build targets, dependencies, variables, and phony tasks used to automate builds and workflows.
2 PagesIntermediateFeb 18, 2026
Basic Syntax
Targets, prerequisites, and recipes.
makefile
# target: prerequisites#\trecipe (must be indented with a TAB, not spaces)app: main.o utils.o gcc -o app main.o utils.omain.o: main.c gcc -c main.cutils.o: utils.c gcc -c utils.cclean: rm -f *.o app
Phony Targets & Variables
Common conventions for non-file targets.
makefile
.PHONY: build test cleanCC := gccCFLAGS := -Wall -O2SRC := $(wildcard *.c)OBJ := $(SRC:.c=.o)build: $(OBJ) $(CC) $(CFLAGS) -o app $(OBJ)test: build ./run_tests.shclean: rm -f $(OBJ) app
Automatic Variables
Special variables available inside recipes.
- $@- The name of the current target
- $<- The first prerequisite
- $^- All prerequisites, space-separated, duplicates removed
- $?- Prerequisites newer than the target
- %.o: %.c- Pattern rule: builds any .o from a matching .c file
- .DEFAULT_GOAL- Overrides which target runs when 'make' is called with no arguments
Real-World Example
A typical Node/Docker project Makefile.
makefile
.PHONY: install build docker up downinstall: npm cibuild: install npm run builddocker: docker build -t myapp:latest .up: docker compose up -ddown: docker compose down
Pro Tip
Always declare non-file targets like 'clean' and 'test' under .PHONY — without it, Make will skip the recipe if a file literally named 'clean' ever exists in the directory.
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