Assembly Optimization Basics

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Why Hand-Optimize Assembly

Modern compilers with -O2/-O3 already perform strong optimizations, so hand-written assembly is reserved for cases where the compiler provably falls short: tight inner loops in codecs, cryptographic primitives needing constant-time execution, or SIMD kernels using intrinsics the compiler won't auto-vectorize reliably. The first rule of assembly optimization is measurement — profile with tools like perf stat to find actual hot paths before touching any instruction, because optimizing cold code wastes effort and adds maintenance risk for zero benefit.

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Cricket analogy: Optimizing assembly without profiling first is like a captain changing the field for every single delivery instead of studying where the batter actually hits most often — you fix problems that don't exist while missing the real scoring zones.

Instruction Selection and Latency

Not all instructions that compute the same result cost the same cycles: on modern x86 cores, imul has noticeably higher latency than add or lea, so multiplying by a small constant like 5 is often faster expressed as lea eax, [eax + eax*4] than as imul eax, eax, 5. Similarly, xor eax, eax is the idiomatic and fastest way to zero a register — it's recognized by the CPU's zero-idiom detection and doesn't even consume an execution port on many microarchitectures, unlike mov eax, 0 which does.

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Cricket analogy: Choosing lea over imul for a multiply is like a batter picking a controlled paddle sweep over a big slog when both score the same runs but the sweep carries far less risk of getting out.

asm

; Multiply eax by 5 without imul, using lea's address-calculation hardware
lea eax, [eax + eax*4]   ; eax = eax*5, no imul latency

; Idiomatic zero (recognized by zero-idiom detection on modern x86)
xor eax, eax             ; faster and smaller than: mov eax, 0

Loop Unrolling and Reducing Branch Overhead

Loop unrolling reduces the relative cost of branch instructions and loop-counter bookkeeping by processing multiple elements per iteration — for example, unrolling a 4-byte-at-a-time copy loop to handle 16 bytes per iteration cuts the number of dec/jnz branch pairs executed by 4x. This trades code size and register pressure for fewer branch mispredictions, but over-unrolling can hurt instruction-cache locality, so the unroll factor should be tuned against measured cache behavior rather than maximized blindly.

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Cricket analogy: Loop unrolling is like a bowler delivering a set of four balls per over-planning cycle instead of reconsidering the field after every single ball, cutting down repeated decision overhead.

Use perf stat -e branch-misses,instructions,cycles to check whether a loop unrolling change actually reduced branch mispredictions before committing to it — intuition about instruction counts often doesn't match measured cache and predictor behavior.

Avoiding Pipeline Stalls and False Dependencies

Partial register writes create false dependencies on out-of-order x86 cores: writing to al without clearing the upper bits of eax first can force the CPU to stall waiting for the previous full-register value, a hazard avoided by zeroing with xor eax, eax before writing al. Similarly, chains of dependent instructions (each waiting on the previous result) limit instruction-level parallelism regardless of how many execution ports the CPU has, so restructuring code to interleave independent operations — for example alternating updates to two accumulator registers instead of one — lets the out-of-order scheduler exploit more parallelism.

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Cricket analogy: A false register dependency is like a batting partnership where the non-striker refuses to run until checking an old, already-superseded scoreboard reading, stalling a run that should've been free.

Micro-optimizations like these are microarchitecture-specific: an instruction sequence tuned for one CPU generation (e.g., avoiding partial-register stalls on an older Intel core) can be neutral or even counterproductive on a newer core with different renaming logic. Always re-benchmark on the actual target hardware.

Profile with tools like perf before hand-optimizing; only touch measured hot paths.
Prefer low-latency instructions like lea for small multiplications and xor reg,reg for zeroing over imul/mov reg,0.
Loop unrolling reduces branch overhead per element processed but must be tuned against instruction-cache effects.
Partial register writes (e.g. writing al without clearing eax) can cause false dependencies and pipeline stalls.
Interleaving independent operations across multiple accumulators can expose more instruction-level parallelism to out-of-order execution.
Micro-optimizations are microarchitecture-specific and must be re-validated on the actual target CPU.
Hand-written assembly should be reserved for cases the compiler demonstrably cannot handle well, such as constant-time crypto or manual SIMD.